Tom’s Circuits – Design to Avoid EMI Problems: Keep Clocks Away from Unintended Antennas

January 12, 2018 , in Blog, Tom's Circuits

Unwanted PCB antennas can cause FCC EMI testing failures. Careful circuit design and board layout will minimize these problems. While many EMI problems can be eliminated with simple design changes, others require adding circuit components and some involve mechanical changes such as adding shielding. Changes late in the design process such as copper tape, spring fingers, and new product tooling are expensive. You can avoid these costs by developing expertise in design-for-EMI, getting the right equipment, and testing early in the design process.

Start with a dipole antenna.

Dipole antenna

When the arms of the antenna have a different voltage, it creates an electromagnetic field:

Dipole electromagnetic field

The electric field lines are painted in the picture with darker colors for a more intense field. The picture shows a miniature version of the larger field, and how it is oriented relative to the antenna. The electric field goes along the colored lines, where current flows between the arms due to capacitance. The magnetic field is perpendicular to these lines and runs around the tread of the tire shape. This is the ideal case—in the real world there are surrounding objects that distort the shape of the field.

Many antenna designs can be translated to an equivalent dipole. A good way to learn to spot EMI problems is to see the design patterns that create dipoles. For example, adding a sheet of metal between the arms of the dipole creates a mirror.

Dipole creates a mirror

The dipole arm in the mirror causes the same field shape that a real dipole arm would cause. This configuration is called a monopole and it usually drawn in the other orientation.

Monopole field

The monopole field is stronger because the energy is concentrated above the plate, instead of being spread across both sides of the dipole.

Any wire can become a monopole, because any nearby metal can act as the other half of the antenna. Many products with plastic cases add metal to make the monopoles predictable. This metal can be a sheet of foil or a conductive coating, as large as will fit. This intentional reference plane improves the reproducibility of EMI tests.

Printed circuit board traces running over solid ground planes rarely cause EMI problems. Exceptions to this include digital clocks and switching power supplies. These signals always show up on EMI reports.

EMI report

This is a typical emissions graph from an EMI report. This product passes the FCC Class B radiated emissions test, because the blue line is below the Class B limit with 6dB of margin. The extra margin allows the test lab to certify the design using an indoor anechoic test chamber, rather than having to use an outdoor antenna range. Passing EMI inside a test chamber saves test time and money.

From 30MHz to 50MHz, the graph shows a combination of data bus noise and switching power supply clocks. Since data signals change in a random way, the spectrum is spread and the emissions are relatively low. The narrow signals at higher frequencies are clock signals. Since they are continuous tones, their spectrum is a spike in the emissions graph, and they stick up from the other more random signals. The wider spikes in the frequency display are radios of some sort, with their spectrum spread out by modulation.

The log frequency graph is required for the FCC report, but when diagnosing these problems, it is more common to look at linear frequency sweeps on a spectrum analyzer.

Clock spectrum analyzer

On the linear graph, the clock shows up as evenly spaced signals, usually with stronger odd harmonics. Along with the switching power supply harmonics, these clock harmonics cause most EMI problems. For EMI purposes, it would be better to have a slower clock edge. For high-speed digital designs, measuring clock edges and understanding clock distribution is challenging. For example, in this simulated waveform, there are several clock traces with different impedances and two vias connecting a clock to two different loads.

Simulated waveform

While the waveform doesn't look too bad when measured with a 100 MHz oscilloscope, the 1 GHz oscilloscope reveals severe problems with the waveform that can lead to difficult to troubleshoot problems such as double triggering.

A better solution is to use short traces and a single load for each output from a clock driver buffer amp. Use a high-speed oscilloscope and voltage probe to measure fast rise times, and use a spectrum analyzer with a small loop antenna to debug EMI problems. EMI and signal integrity need separate analysis and measurements.

One common clock EMI layout problem happens when a printed circuit board trace goes over a slot in a ground plane.

PCB trace goes over a slot in a ground plane

The current from the source flows in a loop, and at high frequencies, it follows the path of least inductance. There should be a solid ground plane underneath the trace, but a slot in the plane causes the return current to flow around the slot. Slots make great antennas, and create similar fields to monopoles and dipoles that have the same shape as the slot.

The best fix for this problem is to have a solid ground plane, but a bridge in the slot will help. The width of the bridge should be at least the width of the trace plus ten times the height of the trace above the ground plane.

PCB trace goes over a bridged slot in a ground plane

Long clock traces need to be avoided, and other traces need to be kept away from the clocks. Other traces tend to pick up clock signals and take them everywhere, contaminating the whole system. To achieve a good PCB design, place the parts and route the clocks first, optimizing for the shortest clock trace lengths. Establish keepout areas and use solid planes. Don't leave ungrounded regions of floating copper fills in the layout. Use many vias to connect grounds between layers together.

The further the clock travels away from the ground return path, the worse the EMI problem is. Tall packages create a monopole antenna.

Monopole antenna

The clock trace is short, and the fields are confined to near the trace, but the package lifts the clock signal off the board and creates a larger loop. Clock driver chips in QFN packages ride lower on the board. A noisy-package problem like this can be diagnosed with copper tape and a capacitor. Connect wires from the copper tape to all the IC ground pins, and add bypass capacitors from the copper tape to the power supply pins.

Copper tape and a capacitor

This modification also improves power supply bypassing, which is needed to prevent the pulsed currents drawn by clock circuits from creating clock ripple voltage on the power supply.

Keep clock signals away from the edge of the PC board. Only route clock signals adjacent to ground planes, not power supply planes.

Minimize the number of vias on the clock trace. When it is necessary to route clock signals between layers, surround the clock via with ground vias. This shields the via and provides a short return path for ground current. Without these nearby vias, the return current will flow through one or more further-away ground vias, spreading out the clock current and contaminating other signals.

EMI test limits are designed to keep electronic products from interfering with other products that contain radios. Products that include a radio are even more sensitive over the receiver frequency range and require extra shielding, grounding, and bypassing.

Even with careful design, EMI surprises can crop up late in product development and require a fast PCB redesign and retesting. Tempo Automation provides fast, reliable turnaround, allowing you to iterate redesigns quickly and get you back on schedule!


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