Effectively Using Layout Versus Schematic (LVS) Simulation for Your PCBA Design

May 14, 2020 , in Blog

Once upon a time, a person's word was all the verification one needed. However, in today’s world, that concept sounds like a line out of a fairytale, and rightfully so, because verification is not just a matter of subjective belief anymore. These days, it isn’t considered safe to even visit a doctor without researching and verifying their credentials. And in terms of PCBs, verification is a crucial step required to ensure plans and schematics reflect the designer’s intent and obtain valuable information about the PCB layout that can be used to correct errors and adhere to the tolerances specified by a contract manufacturer (CM).

Electronic product design concept PCB in front of schematic capture

What is Layout Versus Schematic (LVS)?

The Layout Versus Schematic (LVS) is a class of electronic design automation (EDA) verification software used to determine if a specific integrated circuit or board layout correlates with the original circuit diagram, or schematic, of the design. In other words, it is a method of verifying if the layout of the design is functionally equivalent to the design schema.

A successful design rule check (DRC) confirms that the layout adheres to the rules of the design and the requirements necessary for error-free fabrication. However, it does not certify whether it actually represents the specific circuit you wish to fabricate. This is precisely why there is a need for the effective use of LVS verification.

The necessity of such programs was universally accepted early on in the history of integrated circuits. Examining the history of similar programs, the origins of LVS date to as far back as 1975. The earlier iterations of these similarly functioning programs operated mainly on the premise of graph isomorphism, which is a methodology that involves verifying whether the layout and the schematic were virtually identical.

With the onset of digital logic, these earlier iterations were deemed too restrictive, as you could implement the same functions in various non-isomorphic ways. This limitation prompted the augmentation of LVS utilizing formal equivalence checking, which is a check that discerns if two circuits perform the same precise function without requiring isomorphism.

How to Effectively Use Layout Versus Schematic (LVS)

At a high level, the LVS software checks and identifies the illustrated shapes of the layout that represent the electronic components of the circuit, including the connections between them. Furthermore, the LVS software compares this netlist against a similar schematic or circuit diagram's netlist. In summary, the effective use of LVS checking incorporates the three following steps.

1. Extraction: In this first step, the LVS software utilizes a database file that contains all of the layers drawn to symbolize the circuit during layout. Next, it runs the database through various area-based logic processes to ascertain the semiconductor components expressed in the drawing by their layers of construction. These area-based logical procedures utilize polygon-areas as inputs and then generate output polygon-areas from those operations.

Using these operations, the LVS software defines the terminals of these devices, the device recognition layers, the via structures and wiring conductors, as well as the pin locations (hierarchical connection points). The layers indicating proper wiring or conductors are typically called and made up of metals. However, the vertical connections between these layers are generally called vias.

2. Reduction: In the second step, the LVS software coalesces the extracted components into parallel and series combinations if possible, thus generating a netlist that represents the layout database. Additionally, it performs a similar reduction process on the schematic (source) netlist.

3. Comparison: In the third step, the LVS software takes the extracted layout netlist and compares it to the netlist taken from the circuit schematic. If these two netlists match, then the circuit in question passes the LVS check and is considered “LVS clean.”

Note: Mathematically speaking, the comparison between the schematic and layout netlists is made possible by performing a graph isomorphism check to ascertain if they are equivalent.

What are the Typical Errors Associated With LVS?

Overall, in most cases, the layout will not pass LVS on the first attempt. This failure requires the engineer to examine the LVS software's reports further to make necessary changes to the layout. The following are the typical errors one encounters during LVS.

  • Shorts: This, of course, is when there are two or more wires that are making conductive contact that should be and thus must be separated.
  • Opens: This is when components or wires that should be connected or making conductive contact are not connected or are partially connected. The understood remedy here is to correct the connection issue by correctly connecting the wires or components.
  • Component Mismatches: This occurs when you use an incorrect component type, such as a low voltage threshold transistor instead of an ultra-low voltage threshold transistor.
  • Missing Components: This one is self-explanatory, as it pertains to actual missing components left out of the layout.
  • Parameter Mismatch: In the field of electronics, parameters are a necessary measure to ensure components and devices alike meet functional tolerances as well as performance. Moreover, the components in your netlist can and will contain properties that correlate with these parameters. Furthermore, it is possible to configure the LVS to identify these parameters or properties up to a predetermined tolerance level.

If the component or device fails to meet this tolerance, then the LVS check will deem this as a Property Error. Although the checked parameter may not be an exact match, it can still pass if it is within the LVS tolerance. For example, if your schema indicates that you are using a 2KΩ resistor and the extracted netlist has the matched resistor rated at 1997 ohms, it would still pass if the tolerance is set at 3%.

In conclusion, verification is an essential part of the design process, and software such as LVS provides the tools to assess the correctness of the design accurately.

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A knowledgeable CM like Tempo Automation can help you optimize the verification process and ensure your layout matches the intended design. We work with you from day 1 of design to maximize your chances of developing a PCB that functions and performs as intended.

And to help you get started on the best path, we furnish information for your DFM checks and enable you to easily view and download DRC files. If you’re an Altium Designer or Cadence Allegro user, you can simply add these files to your PCB design software. For Mentor Pads or other design packages, we furnish DRC information in other CAD formats and Excel.

If you are ready to have your design manufactured, try our quote tool to upload your CAD and BOM files. If you want more information on effectively using layout versus schematic (LVS) simulation for your PCBA Design, contact us.

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